Timing Violation Error After Compiling the Example of NI-6583

Issue Details

I'm using the NI 6583 Continuous Acquisition DDR - External Clock example with PXI-7972R but I got a timing violation error during compilation. The external clock is smaller than 200MHz.

Solution

You can follow the steps below to modify the default 200MHz timing constraint:

1. Open the .ucf file which constrains your CLIP.  You will start at this location: C:\Program Files (x86)\National Instruments\Shared\FlexRIO\IO Modules\NI 658X (where X is the module you are using)
2. The .ucf will be under the CLIP you are using, which can be found in the LabVIEW project explorer, and the version of that CLIP.  An example .ucf name for the NI 6585: Ni6585.ucf
3. Edit the value of the property listed below in the CLIP.  These additional notes are also located inside the CLIP file.  For example, for the NI 6585:

# Clock Period Constraint (200MHz)
# This constraint affects IO Module Clock 0, which coresponds to the DDCA Clock.
# To reduce the constraint, change '5 ns' to the worst case period of your
# external clock.

NET "UserGClkLvttl" TNM_NET = "DDCAClock";
TIMESPEC "TS_DDCAClock" = PERIOD "DDCAClock" 5 ns HIGH 50%;

# Clock Period Constraint (200MHz)
# This constraint affects IO Module Clock 1, which coresponds to the DDCB Clock.
# To reduce the constraint, change '5 ns' to the worst case period of your
# external clock.

NET "UserGClkLvds" TNM_NET = "DDCBClock";
TIMESPEC "TS_DDCBClock" = PERIOD "DDCBClock" 5 ns HIGH 50%;

4. Save the .ucf and recompile your code.  The constraint will now be updated.

Note:

• If you are using FlexRIO devices with K7 FPGA, then you will need to find xxxxTiming.xdc file instead of .ucf file. For example for the NI 6583, the file name will be NI6583Timing.xdc. The content to be modified is the same as described above.
• You might need to modify the CLIP declaration XML file as well:

1. Open the NI685x[ClipName].xml located in C:\Program Files (x86)\National Instruments\Shared\FlexRIO\IO Modules\NI 658X using Notepad or XML Notepad .
2. Modify the maximum frequency of Strobe to value that matches the timing constraint.

  <FreqInHertz>
    <Min>100</Min>
    <Max>200M</Max>
  </FreqInHertz>​​​​​​

3. In LabVIEW Project Explorer, open IO Modules Properties. Click on the Refresh icon and close the properties windows. Locate the Strobe channel under IO Module and open the properties windows. Check if the maximum compilation frequency has been update.

Additional Information

NI has identified a potential issue with the HSDIO family of FlexRIO Adapter Modules (NI 6581, 6583, 6584, 6585, 6587) and the specific use of an external clock for these modules. These external clocks were unconstrained in the compiler, which could lead to data integrity issues. The course of action NI has taken for this particular issue is to add "worst-case" timing constraints to all CLIP files for all HSDIO FlexRIO Adapter Modules in NI FlexRIO Adapter Module Support 3.3 or later. This causes an error to be displayed if the combination of external clock frequency plus compilation timing does not match up.

The effect of this addition to the CLIP means that your compilation may unnecessarily fail if your external clock is not maximum frequency.  The recommendation for cases in which timing may pass if the timing constraints were changed is to enter the CLIP and change the file.