Timing Violations Errors During FPGA Compilation

Updated Jan 11, 2019

Reported In


  • cRIO-9063
  • cRIO-9030


  • LabVIEW FPGA Module
  • LabVIEW

Issue Details

I'm getting timing violation errors when compiling my FPGA code for deployment. I'm not using any single-cycle timed loops in the code but I keep getting errors during compilation that state that I'm not meeting timing requirements.

My error looks somewhat like this:


Try to optimize the FPGA code for speed by following the steps laid out in the Optimizing FPGA VIs for Speed and Size LabVIEW FPGA Module help documentation.

If working through those speed optimization options don't resolve the timing violation, try and optimize the FPGA code for size as well. Larger FPGA bitfile sizes can negatively affect routing on the FPGA which can cause timing violations.

Additional Information

If you have the Xilinx Compilation Tools installed locally or on a remote compiler, you can also change the Xilinx build options from "Default" to "Optimize Congestion" in the build settings of your project. This will also assist with FPGA routing.


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