Timing Violations Errors During FPGA Compilation

Updated Apr 15, 2020

Reported In


  • cRIO-9063
  • cRIO-9030


  • LabVIEW FPGA Module
  • LabVIEW

Issue Details

I'm getting timing violation errors when compiling my FPGA code for deployment. I'm not using any single-cycle timed loops in the code but I keep getting errors during compilation that state that I'm not meeting timing requirements.

My error looks somewhat like this:


  1. If you have the Xilinx Compilation Tools installed locally or on a remote compiler, change the Xilinx build options from Default to Optimize Congestion in the build settings of your project to assist with FPGA routing. 
  2. If you have Standard Service Program (SSP) for software please try using the NI LabVIEW FPGA Compile Cloud Service.
  3. If you don't have SSP, or you receive the errors when using the Compile Cloud, please optimize the FPGA code for speed by following the steps laid out in the Optimizing FPGA VIs for Speed and Size LabVIEW FPGA Module help documentation.
  4. If working through the speed optimization options doesn't resolve the timing violation, try and optimize the FPGA code for size as well. Larger FPGA bitfile sizes can negatively affect routing on the FPGA which can cause timing violations.