Error Compiling NI 6583 Shipping Example for FlexRIO 7962R

Updated Jun 4, 2018

Reported In


  • PXIe-7962
  • NI-6583


  • LabVIEW 2017 Professional
  • LabVIEW 2017 FPGA Module
  • LabVIEW 2017 SP1 Professional
  • LabVIEW 2017 SP1 FPGA Module
  • LabVIEW 2015 Professional

Operating System

  • Windows


Windows 7 Professional
Windows 7 SP1
Windows 10

Issue Details

When trying to compile the LabVIEW shipped example project NI 6583 Continuous Generation DDR-internal Clock with a derived clock of 150 MHz or 100 MHz from the parent clock 40 MHz, the compilation fails due to a Xilinx error with both local compiler and cloud compilation:



This is a bug related to the VHDL of the adapter CLIP where the ODDR signal is being routed back into the FPGA fabric when using a derived clock. However, there is a workaround for this issue by using Base Clock instead of Derived ones:
  1. Add the 100 MHz Base Clock.  In the Project Explorer, Right-click the PXIe-7962R >>  New >> FPGA Base Clock.
  2. Under Resource choose 100 MHz Clock.
  3. Right-click IO Module >> Properties
  4. In the Clock Selections tab of IO Module Properties, connect the top 4 clocks to 100 MHz Clock as well.
  5. Open  the FPGA VI NI 6583 Continuous Generation DDR-Internal Clock VI then on the Clock input node of the SCTL choose 100 MHz Clock instead of 100 MHz.

This will allow you to compile the code for the Base Clock option (100 MHz) as the adapter supports only up to 150 MHz thus the option 200 MHz cannot be used in this case.


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