This content is not available in your preferred language.

The content is shown in another available language. Your browser may include features that can help translate the text.

Viewing the Last "Successful Compile Report" from the LabVIEW FPGA Module

Updated Feb 29, 2024

Reported In

Software

  • LabVIEW FPGA Module

Issue Details

After a successful LabVIEW FPGA compilation, I see the Successful Compile Report for the Compile VI. If I clicked Close or OK and did not save the report, where can I access the details of this report again?

Solution

LabVIEW 2010 and Newer:

The addition of Build Specifications for LabVIEW FPGA VIs in LabVIEW 2010 has made it more convenient to access the results of the most recent compilation. To access these results, simply right-click on your FPGA VI's Build Specification and select Display Compilation Results.
 
Selecting this option will display the Compilation Status window for the latest compilation, successful or not. This status window also changed for LabVIEW 2010, with multiple reports for estimated and final device timing and utilization.
 


The log is also accessible at the following path. However, these logs are less formatted and more difficult to read.
<maindrive>:\NIFPGA\Compilation\yourprojectname_yourtargetname_yourbuildspecname_compilercode

LabVIEW 2009 and Older:

To access the compilation logs, right-click the FPGA VI and select Target-Specific Properties. The properties window displays the latest compilation report details under Compile Results, as seen below.


The FPGA Device Utilization Summary is also stored in the log files generated by the Xilinx Compiler. The log file for the compile can be found in the root path for the Xilinx Compiler.
C:\NIFPGAx\srvrTmp\localhost\<your project folder>\toplevel_gen_xst.log

The x in NIFPGAx corresponds to the version of the LabVIEW Compile Server, i.e. NIFPGA86 for LabVIEW 8.6.

The Device Utilization Summary can be found in the Final Report section of the log file. This file also contains various synthesis metrics such as a Timing Report and Propagation Delays for the different logic paths synthesized on the FPGA.

A sample
top_level_gen_xst.log file is attached to this document. If your default text editor does not display the log file in a readable format, open it with another word processing program.