It is not possible to run the Primary Control Loop (PCL) of the VeriStand Engine at 1 MHz, and model loops are run at the same rate as the PLC or at a slower decimated rate. This limitation is due to various operation that must be completed each iteration of the PCL
and the inherent overhead present for the VeriStand engine to iterate the loops and keep track of timing. Trying to set a PCL too fast will result in the VeriStand Engine's loops finishing late and will impact the determinism of the system. There is a possibility of achieving rates of 1MHz or higher for simulation models in HIL systems by utilizing FPGA devices. The FPGA code for the model could be developed in LabVIEW FPGA, or it is possible to export Simulink models into HDL code that can then be used in a LabVIEW FPGA VI. Refer to the Related Links section for more information.
There are various methods of utilizing custom-developed FPGA code
and making inputs and outputs available for configuration and execution in the VeriStand Engine. For example, the FPGA Add-On custom device gives users a simple method for executing custom FPGA code in VeriStand using FPGA devices. It supports both single-point and waveform data channels. Note that a developing custom device for VeriStand is an advanced topic and requires a deep knowledge of Real-Time, FPGA systems and VeriStand Engine.NI Engine Simulation Toolkit for NI VeriStand
is the example of implementing simulation model on FPGA.