Why Do I Need to Run My FPGA VI Every Time Manually for My NI cRIO Target?

Issue Details

I am working on NI cRIO-9068. A part of my functionality resides on FPGA while rest of it is on real-time (RT) processor. I have used "Open FPGA VI Reference" on RT VI to load FPGA bitfile. However, whenever I try to run RT VI, the controls showing FPGA data never get updated, unless I manually run FPGA file from project.

Solution

This behavior can arise because of following reasons:

1. Please be sure that "Run the FPGA VI" option is checked in "Open FPGA VI Reference" configuration dialog. Alternatively, you can use "Run" invoke method to perform this task. While using this invoke method, setting "Wait Until Done (F)" to "True" value will ensure that your RT code will wait until FPGA bitfile is deployed on target successfully.

2. Please be sure that if you are using cSeries modules in hybrid mode, you are following correct step sequence for configuration. You can find this knowledge base useful to know more about this.

3. Please make sure that there is no error occuring on FPGA VI once you load FPGA VI from RT using "Open FPGA VI Reference" function. This can be one of reason for halting FPGA code from proper functionality. Errors can occur because of incorrect settings being deployed from RT, configuration issues, etc. Please use debugging tools for NI LabVIEW FPGA to check for any such issues.