Simulink Compilation Error When Creating Model Containing a Bus Array for Veristand

Updated May 27, 2020

Reported In

Software

  • VeriStand 2017
  • VeriStand 2018 SP1
  • MATLAB

Issue Details

I am getting a Simulink® compilation error when using bus creator in model with VeriStand 2017. The error message is shown below: 

Root level output logging in 'Dataset' format is not supported in this simulation or code generation mode for model 'DebugBusCompileError_2'. No data will be logged. To log root level output data, set ''Configuration Parameters > Data Import/Export > Format'' parameter to 'Array', 'Structure', or 'Structure with time'.

How to fix the error if I want to still use the bus creator? 

Solution

You need to upgrade VeriStand to 2018 SP1 or a higher version.
Since VeriStand 2018 SP1, a toggle was added to revert to the previous behavior of ignoring bus arrays that were not defined.
The checkbox is found in the "Configuration Parameters" dialog box under "Code Generation" -> "NI Configuration" -> "Disable exporting of Bus Arrays". 
 

Additional Information

Note:
The "Disable exporting of Bus Arrays" prevents anything that is inside a bus from being shown in VeriStand, so inports, outports, and signals that use buses won't be available as a channel in Veristand. But they will still work internally in the model so they only can't be used for anything in Veristand.

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