Issue Details
I'm doing a simple design in Multisim that uses the d latch but it is giving an error when deploying to an FPGA target:

I'm following the procedure from
Export Digital Logic to Xilinx FPGAs With NI Multisim but it is giving me the following error even when it passes the topology check:
PLCK-12#1 Error
Clock Placer Checks
Poor placement for routing between an IO pin and BUFG.
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several
things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be
caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of
the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
I've found some information on the error, but it doesn't give me any indications on how to solve it.
- Why is this error happening?
- How can I edit the design so it will be able to compile?