Error When Deploying a Design with a D-Latch to an FPGA Target in Multisim

Issue Details

I'm doing a simple design in Multisim that uses the d latch but it is giving an error when deploying to an FPGA target:


I'm following the procedure from Export Digital Logic to Xilinx FPGAs With NI Multisim but it is giving me the following error even when it passes the topology check:

PLCK-12#1 Error
Clock Placer Checks
Poor placement for routing between an IO pin and BUFG.
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several
things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be
caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of
the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.

I've found some information on the error, but it doesn't give me any indications on how to solve it. 

• Why is this error happening?
• How can I edit the design so it will be able to compile?

Solution

This error happens because the "EN" enable input will only accept inputs with a high or low value. Buttons and switches can be on the unknown state and this causes the compilation to not go through. 

You can add some additional logic to define the state of the enable pin.


Note: This is not recommended as it can introduce significant delays when running the design for long periods of time.
 

Additional Information

• A D latch is like an S-R latch with only one input: the “D” input. Activating the D input sets the circuit, and de-activating the D input resets the circuit. Of course, this is only if the enable input (E) is activated as well. Otherwise, the output(s) will be latched, unresponsive to the state of the D input.
• D latches can be used as 1-bit memory circuits, storing either a “high” or a “low” state when disabled, and “reading” new data from the D input when enabled.