Error -200714 When Deploying VeriStand Project

Updated Jan 12, 2021

Reported In

Hardware

  • PXIe-4300

Software

  • VeriStand

Issue Details

My VeriStand project System Definition File (SDF) has a PXIe-43xx card configured and uses an inline custom device. When I deploy the project, I get the following deployment error:

The VeriStand Gateway encountered an error while deploying the System Definition file.

Details:
Error -200714 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> Project Window.lvlib:Connect to System.vi

Possible reason(s):

Acquisition has stopped because the driver could not transfer the data from the device to the computer memory fast enough. This was caused by computer system limitations.

Reduce your sample clock rate, the number of channels in the task, or the number of programs your computer is executing concurrently.

Solution

Open your project's System Definition File and look at the Chassis page. If the Chassis master hardware synchronization device is set to None, try using hardware timing instead by selecting one of your cards in the chassis to be the Chassis master hardware synchronization master device. The Chassis master hardware synchronization device is generally a DAQ card or FPGA card:
 
This will configure the single-point acquisition in the VeriStand project to be hardware-timed and synchronized to the clock of the specific master device, which can often resolve timing errors during deployment.

If the issue is still present after setting one of your cards as your master synchronization device, you should try adjusting the Slow Background Conversion Mode sample rate. This value is set by default to -1, which corresponds to dynamically determining the sample rate - try setting this to a fixed value, like 1Hz or 100Hz, depending on the requirements of your application.