Solution
This error can occur if there is no DAQ device set to be the Chassis master hardware synchronization device.
- Open your project's System Definition File and look at the Chassis page
- If the Chassis master hardware synchronization device is set to None, try using hardware timing instead by selecting one of your cards in the chassis to be the Chassis master hardware synchronization master device
- In the Chassis master hardware synchronization device dropdown, select DAQ. If the DAQ option is greyed out, ensure that you have a DAQ card added to the project, that it is configured to be in single-point mode, and that it has at least one analog input or analog output channel added.
- In the DAQ device dropdown, select the device you want to use as the synchronization master
This will configure the single-point acquisition in the VeriStand project to be hardware-timed and synchronized to the clock of the specific master device, which can often resolve timing errors during deployment.
In some cases, a SDF corruption could prevent you from selecting your DAQ card as the Chassis master hardware synchronization device even if the DAQ card is added to the SDF and has at least one single-point analog input or output channel. If that occurs, delete the DAQ card from the project, save the system definition file, and then re-add the DAQ card and channels. After this, you should see the option to use that device as the chassis master hardware synchronization device.
If the issue is still present after setting one of your cards as your master synchronization device, you should try adjusting the Slow Background Conversion Mode sample rate. This value is set by default to -1, which corresponds to dynamically determining the sample rate - try setting this to a fixed value, like 1Hz or 100Hz, depending on the requirements of your application.