Solution
Open your project's System Definition File and look at the
Chassis page. If the Chassis master hardware synchronization device is set to None, try using hardware timing instead by selecting one of your cards in the chassis to be the Chassis master hardware synchronization master device. The Chassis master hardware synchronization device is generally a DAQ card or FPGA card:
This will configure the single-point acquisition in the VeriStand project to be hardware-timed and synchronized to the clock of the specific master device, which can often resolve timing errors during deployment.
If the issue is still present after setting one of your cards as your master synchronization device, you should try adjusting the Slow Background Conversion Mode sample rate. This value is set by default to -1, which corresponds to dynamically determining the sample rate - try setting this to a fixed value, like 1Hz or 100Hz, depending on the requirements of your application.