VeriStand PCL Miss Timing With FPGAs and HP Count Increases Every Cycle

Updated Jul 5, 2024

Reported In

Software

  • VeriStand
  • LabVIEW FPGA Module

Issue Details

I have created a custom FPGA personality for a PXI FPGA card and am using it in VeriStand.  When I use one of these FPGA modules in my system, it works flawlessly.  However, once I put two or more of these cards with the same personality in the chassis, I miss every single PCL cycle and my HP count goes up each cycle.

Solution

  • Try using the default personality for your FPGA card, if there is a default personality for VeriStand.
  • Check to make sure that you are using the correct Timing VIs for your platform.  In this case you are using the PXI platform, so your Timing VIs should be PXI Timing VIs.
    • Here is an example of the default Timing VIs when creating a FPGA VeriStand VI. 
    • Here are the correct VIs, highlighted, for the PXI based FPGAs 

Additional Information

This issue also can happen when one FPGA devices added into the VeriStand if using incorrect Timing VIs for your platform