The FPGA I/O is connected to the RMC connector through a series termination resistor, and the FPGA drive and onboard signal termination support a wide range of applications. In general, this allows RMC implementations to exceed the performance levels (from a digital interface perspective) of an NI C Series module while retaining design flexibility options and robust signal integrity on the RMC.
However, It can be difficult to clearly define the maximum speed of the RMC DIO. Though you can compile the FPGA for relatively high clock rates (40 MHz, 80 MHz, 120 MHz, and so on), this does not mean that the entire signal chain can operate at those rates. Other factors (both on Single-Board RIO controllers and the RMC) such as signal loading, setup and hold times, skew, PCB routing, and lower the effective signaling rate when implementing a particular protocol or interface. Refer to Table for representative applications and typical frequencies that you can readily achieve using common design practices.
This table should not be treated as a guaranteed upper limit. Some applications (due to the implementation of the circuitry on the RMC) may run considerably slower (such as an SPI protocol implemented through slow optoisolators). Other applications (through careful optimization and analysis) may be able to run notably faster.
If you are designing a mezzanine card with very high requirements, please contact NI .