In order to use this line you will be required to route the PFI Line to one of the internal trigger lines available in the cRIO FPGA Line (4 to 7).
In order to read the line you will be required to use the FPGA to read the line using the Trigger line that you have connected to the PFI line. Below is an example:
The PFI line used as a digital input line will require you to send a voltage to the cRIO. Please check the specification of your cRIO for compatible voltage to drive PFI line. Here is an example for Signal input:
Note that the cRIO 9054 will require power and pull up resistor externally to drive the PFI line. No internal configuration to the cRIO is possible to provide pull up resistor and power supply.