Solution
LabVIEW FPGA VIs are reentrant by default. If a reentrant VI is called multiple times, each instance occupies separate hardware resources of the FPGA device. If a non-reentrant VI is used, regardless of whether it is called multiple times in parallel or just once, only one hardware instance is created and used for that VI.
This default behavior is the opposite of VIs running on non-FPGA targets. In this case VIs are non-reentrant by default and there can be only one instance open in memory at one time. All callers must access this same instance. However, when a VI is reentrant on non-FPGA targets, a new instance is opened in memory each time the VI is called.
Reasons to use non-reentrant subVI's:
- To save hardware space and resources on the FPGA.
- Non-reentrant VI's only use a single space in hardware. If space is an issue in your FPGA application, you can put reusable duplicate code into a non-reentrant VI to save space and minimize resource usage.
- Non-reentrant subVI can be used to store and transfer data between independent loops.
- Since the same set of gates are used by all callers of the VI, the values from the last call of that VI are available to the next caller.
Reasons to use reentrant subVI's:
- There is only one instance of a subVI being used in a the main VI.
- When there is only one instance, it makes no difference between either execution mode and no need to change from the default behavior.
- You have the same subVI in two or more independent loops.
- Setting the subVIs as non-reentrant in parallel loops can cause the loops to wait for each other whenever that subVI is called at the same time or called while still executing. This can cause undesired jitter and slow down execution.
- Speed is important and you are not reaching the limit of resource utilization on the FPGA.
- Your program is relatively small but needs to maintain determinism at high frequencies.
- Parallel processes need to have their own instances of the subVI so no data is transferred from one call of the subVI to the next.
More information can be found in the LabVIEW FPGA Help articles listed below.