Using NI 987x Serial Modules in Hybrid Mode on CompactRIO

Updated Jan 10, 2019

Reported In


  • NI-9870
  • NI-9871

Issue Details

I am trying to use my NI 9870 or NI 9871 module on my CompactRIO in Scan Mode while my other modules in the chassis access the FPGA.  When I expand the module in my project, I do not see the ports and I cannot modify the settings for the ports.  How do I discover, configure, and communicate with the serial ports of my NI 987x modules when using the hybrid mode?


To discover and use one of these modules in Hybrid mode follow the steps below:
  1. You must install Scan Engine support for the NI-987x Modules on your Real-Time controller by using a custom software installation. This can be done in NI Measurement and Automation Explorer (MAX) by expanding your Real-Time Target under Remote Systems, right-clicking Software, and selecting Add/Remove Software. Choose Custom Software Installation and click Next. In the Custom software installation window, select the NI-Serial 9870 and 9871 Scan Engine Support.
  1. Add your CompactRIO and Modules to a LabVIEW Project with a hybrid configuration as explained here. Make sure you keep the 987x module under the RT target and this is not dragged under the FPGA. The chassis should be configured for FPGA Interface mode as explained in the article. At this point your project will look similar as the one in the image below:
  1. Run the FPGA VI interactively by clicking the Run Button in the main FPGA VI. After this, you should be able to see the new COM Ports provided by the NI-987x Modules listed in NI MAX and also be able to open a Visa connection from a Real-Time VI.The connection to the serial ports should still be possible even if the FPGA VI has been already stopped. After rebooting the target, you will need to run the FPGA VI again to re-enable the ports. Resetting the FPGA from Real-Time with the corresponding method will also cause the ports to be disabled.

Additional Information

If you are planning to load and run the FPGA VI programmatically from the Real-Time VI using the Open FPGA VI Reference or Run Method, make sure that a considerable delay (at least 2 seconds) is left between the moment when the FPGA VI starts running and when the serial communication is opened with the Visa VIs. This will ensure that the needed intermediate layers are already up and running before trying to stablish communication. Not doing this could lead to error -1073807343 when opening the Visa port.


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