How Can I Optimize FPGA Resource Usage or Speed?

Issue Details

Solution

Reduce gate usage and increase speed: 

• Avoid Large VIs 
  After compiling, a report is generated which provides information on the speed and size of the compiled VI. The Device Utilization Summary section provides information on the number of slices used. This metric is the most important measure of the size of the compiled program on hardware. The design process should be an iterative process. During the process, there may be an increase in the slices used as the program gets larger allowing you to identify when you are running out of space.
• Use Single Cycle Timed While Loop (SCTL) to optimize code
  Any LabVIEW™ FPGA code put into a SCTL is optimized for performance and all extra logic enforcing dataflow is eliminated. Therefore, putting parts of your code into an SCTL and simply wiring a true to the stop condition (runs only once) will create optimized code reducing FPGA Usage and allowing you to specify a clock source for the code.
• Use Appropriate Arbitration
  Shared resources in reentrant subVIs lead to arbitration to prevent race conditions and simultaneous access. Arbitration consumes large amounts of FPGA resources and can impede parallel execution as some parts of your code are unable to proceed until resources are free again.

Only reduce gate usage:

• Eliminate Arrays on the Front Panel
  Arrays on the front panel take up extraordinary amounts of room on the chip as double buffering is required on the FPGA. Front Panel array controls and indicators can be replaced with DMA FIFOs, Block memory instantiation, look up tables, or block diagram constants.
• Minimize Front Panel Elements
  Every element on the Front Panel of an FPGA Main VI creates a register so that the host can communicate and interface with the FPGA. This process uses extra gates on the FPGA to facilitate that communication. If you do not need to use some values to communicate with the host, convert those terminals into constants or global variables.
• Replace arithmetic palette subVIs with binary logic-based calculations
  Function palette subVIs such as Quotient and Remainder, Greater?, and In Range and Coerce can be simplified to binary operations for some cases. This may considerably reduce gate usage on the FPGA, but can require more development time to create.
• Use Block Memory when creating memory items and FIFO's
  When creating memory items and FIFOs for an FPGA Target, there are several implementation choices which can be used to instantiate the item on the hardware. Some of these, such as Flip-Flops or Look-Up Table implementations, use FPGA resources which may be needed for other portions of the FPGA VI. Switching these to use Block Memory implementation will free those resources for use by other portions of the code. Large arrays on the block diagram can also use up these resources, so consider using memory items when you need to store a large array of values.
• Outsource to the Host
  Sometimes you may have implemented functionality on the FPGA which is not required to be implemented there. As such, there may be parts of your program that you can have the host perform and then send the results back through DMA or I/O node communication.
• Split up the FPGA code into parts
  There are times when your FPGA code is simply multiple parts that do not necessarily have to be on the hardware running at the same time. For example, a particular test has four separate test cases. Instead of putting all the cases on the chip in one FPGA program, you can create four separate FPGA programs to download and run as needed from the host.
• Use non-reentrant subVIs
  By default, all LabVIEW FPGA VIs are reentrant, which will result in new resource allocations for each instance of a subVI you use. By switching certain subVIs to non-reentrant, instances of these subVIs all refer to the same hardware instance.

Only increase speed:

• Use Parallel Operations
  One of the main advantages of FPGA programming is the ability to easily create parallel implementations when processing multiple data sets or iterations. By creating parallel instances of portions of your code you can cut down on the overall time needed to perform processing. Since FPGA VIs are reentrant by default, this can be as simple as multiple instances of a subVI running in parallel. 
• Use Pipelining 
  Pipelining allows multiple portions of your code to be running at the same time by dividing sequential processes into discrete steps that can run in parallel. By processing different portions of data this way, the overall speed at which code can run will increase. Use shift registers or feedback nodes to allow logic to execute in parallel and process multiple iterations at the same time. 

For further detail check the NI LabVIEW for CompactRIO Developer’s Guide.

Advanced users may wish to reference the NI LabVIEW High-Performance FPGA Developer’s Guide