Missing Data When Using DMA FIFO With High Sample Rates on FPGA

Updated Apr 4, 2023

Reported In


  • PXIe-7975
  • PXIe-7976
  • PXIe-7965
  • PXIe-7966
  • NI-5782
  • NI-5792
  • NI-5793
  • NI-7931
  • NI-7932
  • NI-7935
  • PXIe-5644
  • PXIe-5645
  • PXIe-5646
  • PXI FPGA Module for FlexRIO


  • LabVIEW Full
  • LabVIEW FPGA Module

Issue Details

I use FlexRIO with an adapter module to collect analog signal. When I set the sample rate higher then 100 MS/s it seems like some data points are missing in the acquired signal. I use a DMA FIFO for data transfer between FPGA Target and Host computer.
100 MS/s:


In this situation the host-side DMA FIFO overflows due to shortage of data throughput.  It will be necessary to increase the transfer speed so as to not overflow the FIFO.

Increasing Throughput:
  • Use optimal data types to transfer data to/from FPGA. For example, If an FPGA target supports transferring unsigned, 32-bit (U32) data through DMA, combine 2 16-bit values to 1 U32 value to transfer it. Refere to your FPGA target documentation for supported transfering data sizes. 
  • Increase Host-side FIFO depth. To do so use FIFO.Configure (Invoke Method) .
  • Increase Number of Elements parameter for FIFO.Read (Invoke Method) .
  • Invoke FIFO.Read (Invoke Method)  more frequently.
  • Put the FIFO.Read (Invoke Method) in it's own while loop to allow it to read at it's fastest rate without additional processing slowing the loop.
  • Increase FPGA-side FIFO depth.
Note:  Increasing FPGA-side FIFO depth will increase FPGA resources utilization and requires recompiling FPGA code.
Utilizing Onboard Memory:
  • Many FPGA devices have onboard memory that you can use to store data until it is ready to be transferred.
  • This will allow the user to acquire data at a rate faster than they can stream samples from target to host as long as there is available onboard memory
  • With FlexRIO devices, DRAM can be used for this purpose