Restarting a CRIO-906x or myRIO Reset and Clears the FPGA , Return I/O to Default State

Updated Jan 10, 2018

Reported In

Hardware

  • cRIO-9067
  • cRIO-9066
  • cRIO-9068
  • cRIO-9063
  • cRIO-9064
  • myRIO-1900

Issue Details

When I restart  cRIO-906x controller or myRIO, the I/O returns to a default state after the FPGA resets and clears. What should I do if I need my I/O to be in a non-default state while the controller is rebooting?

Solution

The cRIO-906x and the myRIO controllers use a Xilinx Zynq System-On-Chip (SOC) which contains the processor and the FPGA fabric in the same die. This means that when your Real-Time processor restarts, the FPGA has to be reset and cleared. The FPGA will be reset and cleared if you reboot using the reset button on the controller, a reset watchdog in your Real-Time VI or your FPGA VI, or if you restart it from MAX. 
  • To keep the FPGA running after you halt your Real-Time executable, you need to end the executable without restarting the target. Since the cRIO-906x and myRIO controllers are running NI Linux Real-Time, shell scripts can be used from within your Real-Time VI to end the current Real-Time executable and start it again.
 
  • If you are using a Real-Time or FPGA watchdog in your code, you may need to modify your executable sequence. Most Real-Time watchdog code uses the RT Watchdog VIs . If you need want to shut down your Real-Time executable without restarting your controller or if you need to run your FPGA code through a shutdown process, then you will need to set up your Watchdog Configure VI to set an occurrence instead of rebooting the controller when the Watchdog timer expires. That way when the occurrence fires, you can control the shutdown procedure for your Real-Time executable. 
 
  • Similarly, if you are writing to the System Reset Chassis I/O item in your FPGA code, your FPGA code will stop executing after you write to that node. If you need to execute a shutdown sequence, do it before writing to System Reset

When the FPGA is cleared, your C Series modules will go into a sleeping state where they output their default values. This is usually a high-impedance state for digital output modules. If you need your digital outputs to enter a different state when the Real-Time controller is rebooting, then you need to use a either a pull-up or pull-down resistor to pull the line to a known state. Ensure that your resistor is large enough so that it does not demand too much current from your C Series module. Analog output modules have various power-on output options. Refer to C Series module specific documentation for more information about C Series module power-on output states and maximum current outputs. 

 

Additional Information

  • To set the FPGA bitfile to run on boot, follow the steps in How Can I Have My FPGA VI Run At Boot? The process of loading and running results in a couple of seconds of downtime where the FPGA I/O is in a default state. National Instruments has measured this downtime at 1.8 seconds, but the delay will vary based on your target and the software you are using. 
  • A common reason to restart a VxWorks or Phar Lap CompactRIO is if your high-priority CPU usage is high enough that your target drops off the network, or fails to execute the lower priority processes for some length of time. However, with the NI Linux Real-Time targets, you do not need to restart your controller if it drops off the network since you can simply end and restart your Real-Time executable in order to free up CPU cycles.

 

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