Synchronizing the 10 MHz Reference Clock on Multiple PXI/PXIe Chassis

Updated Dec 4, 2018

Reported In

Hardware

  • PXI Chassis
  • PXIe-6674T
  • PXIe-6672

Issue Details

I have multiple chassis and want to synchronize the 10 MHz backplane clocks. Is this possible? If so, how can I synchronize the 10 MHz backplane clocks in a multi-chassis system?

Solution

If instead of sharing a reference clock between chassis you want to synchronize to an external Time Reference like GPS, IRIG-B, or IEEE 1588, refer to PXI_CLK10 Disciplining With a Time Reference Across Multiple PXI Chassis.

There are 2 ways that this can be accomplished depending on what's available:

Method 1: External BNC Connectors

The easiest way to synchronize the clocks of two PXI chassis is to connect the PXI_CLK10 OUT of one chassis to the PXI_CLK10 IN of another chassis.

Method 2: Using a Timing Card in the Timing Slot

Use a Timing and Synchronization card in each chassis to export and import clocks.  Consult documentation on the particular timing module in order to configure the device to route the clock as appropriate for your application. 

Additional Information

Using the BNC connectors, when a clock is present it will automatically override the PXI system clock. This introduces a very small time skew between the two clock waveform that is negligible between two PXI systems but will increase when daisy-chaining chassis. To significantly reduce this skew, use an external 10 MHz clock source with equal length cables going to each PXI_CLK10 IN connector.

For the best synchronization of multiple PXI chassis, using a Timing and Synchronization module allows for extremely accurate synchronization between multiple chassis. When the module exports a clock to the PXI chassis, the chassis will automatically use this clock instead of the chassis clock. However, some PXI chassis require manual configuration in order for the module clock in the timing slot to override the the chassis system clock. Be sure to consult the documentation on the PXI chassis to determine the proper configuration for a timing module clock to override the PXI system clock.

Synchronizing a medium amount of PXI chassis may require splitting the timing signals from a master to multiple slaves. Using a passive splitter can degrade the quality of the signal. Timing cards like the PXIe-6674T and PXIe-6672 have programmable thresholds in all their terminals to address this issue. An example of this can be found in Synchronizing Multiple Chassis. Be aware that passively splitting signals into too many channels can degrade the signal too much, even for the programable threshold of timing cards. If you need to split signals between a large number of chassis, you should consider using an active splitter or using a time reference .

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