Solution
There is a known issue with Xilinx Vivado 2015.3 and later when trying to use parentheses in the constraint file (*.xdc) path when programming boards. This can be a problem when using the installed Multisim PLD configuration files on 64-bit versions of Windows because the default installation directory for these files contains parentheses (e.g.
C:\Program Files (x86)\National Instruments\Circuit Design Suite 14.0\pldconfig).
To solve the issue we recommend copying the constraint file you plan to use to a new path that does not contain parentheses, such as the user desktop folder. Then on Step 2 of the PLD Export dialog, you will need to browse to the file under the Advanced settings, Xilinx user constraint files (*.xdc) path: