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Illegal File Name Error When Exporting to PLD from Multisim Using Xilinx Vivado

Updated Apr 4, 2023

Reported In

Software

  • FPGA Xilinx Compilation Tools
  • Multisim Full

Issue Details

When trying to program FPGA boards using Multisim and Xilinx Vivado, I get an error that reads "Illegal file or directory name", even though I am using the standard PLD configuration files installed by Multisim. 

Solution

There is a known issue with Xilinx Vivado 2015.3 and later when trying to use parentheses in the constraint file (*.xdc) path when programming boards. This can be a problem when using the installed Multisim PLD configuration files on 64-bit versions of Windows because the default installation directory for these files contains parentheses (e.g. C:\Program Files (x86)\National Instruments\Circuit Design Suite 14.0\pldconfig). 

To solve the issue we recommend copying the constraint file you plan to use to a new path that does not contain parentheses, such as the user desktop folder. Then on Step 2 of the PLD Export dialog, you will need to browse to the file under the Advanced settings, Xilinx user constraint files (*.xdc) path:

Related Links

Getting Started with Digilent Boards in Multisim

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