High CPU Usage When Reading Data from Target-to-Host DMA FIFOs

Updated Jun 4, 2024

Reported In


  • LabVIEW FPGA Module

Issue Details

I am reading data into my LabVIEW Real-Time VI from an FPGA by using a Target-to-Host DMA FIFO. I can see in the Distributed System Manager that the Real-Time target's CPU usage nears 100%, which is causing my processor to starve, and my other loops are not able to run.


Consider using the following architecture to only read the FIFO when it has samples in it, rather than using a time-out:

Additional Information

Unlike Real-Time FIFOs, which can be configured as polling or blocking, DMA FIFO behavior is determined by the hardware it is running on.

On the majority of National Instruments' Real-Time controllers, DMA FIFOs will poll for new samples when configured with a timeout. This can result in your Real-Time processor experiencing a high load, which can in turn cause undesired execution behavior.

Real-Time Controllers with the NI-STC3 timing engine (e.g. the cRIO-903x series) use interrupts to perform DMA transfers, so you aren't burdening the processor to check if data is ready.

Since this is expected behavior, starvation of other threads is a symptom of an application that needs more careful consideration of thread timing. The appropriate way to resolve this issue is to use a preliminary Target-to-Host FIFO.Read method to programmatically check the DMA FIFO to see if the needed data is available before attempting to read the data, as demonstrated in the solution.