If you are planning to load and run the FPGA VI programmatically from the Real-Time VI using the Open FPGA VI Reference or Run Method, make sure that a considerable delay (at least 2 seconds) is left between the moment when the FPGA VI starts running and when the serial communication is opened with the NI VISA VIs. This will ensure that the needed intermediate layers are already up and running before trying to establish communication. For more details refer to Related links section.
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Using the NI 987x Modules in Hybrid Mode on CompactRIO
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