Solution
The analog frequency you can generate (F
analog) is determined by the update clock frequency (F
update) and number of samples per cycle (S
cycle). The onboard 20 MHz clock that is used to generate F
update can only be divided by an integer.
As an example, if we need to generate a clean sine wave at 2 kHz we would need roughly 50 samples per cycle. Therefore:
Fanalog = Fupdate / Scycle
2 kHz = Fupdate / 50
Fupdate = 100 kHz
Now,
20 MHz / x = 100 kHz
x = 200
This calculation shows that the onboard clock must be divided by 200 to obtain an update clock rate of 100 kHz. The next available update clock we could generate would occur using a divisor of 199 or 201. If we chose 201, it would produce the following results:
Update Clock = 20 MHz / 201 = 99502.48 Hz
Fanalog = 99502.48 Hz / 50 = 1990.05 Hz
The smallest frequency change that we could generate in this case would be approximately 10 Hz. Another limiting factor would be the code width of the DAQ device in use, but this is rarely a factor as most users do not want that many samples to represent a cycle.