VeriStand Suddenly Gets Clock Rate Errors After Adding my First DAQ Device

Updated Nov 21, 2017

Reported In


  • VeriStand Full


  • NI-DAQmx



Issue Details

  • We've recently added a PXI DAQ module to our VeriStand System
  • We have been using R Series cards for our I/O with no issues
  • We are now getting one or both of the following errors:
    • Run-time error -200714 intermittently during deployment:
      • A run-time error has occurred in step: Initialize VeriStand. [...] Acquisition has stopped because the driver could not transfer the data from the device to the computer memory fast enough.
    • Error -209801 intermittently while VeriStand is running
      • DAQmx Write did not complete before the arrival of the next sample clock



Your software loop is not able to keep up with the pace set by your hardware, so you have 3 options
  • Make your software faster by doing less per loop, do things more efficiently, or get a faster controller
    • Lower your Primary Control Loop (PCL) rate till your software loop can consistently keep up
        • You can use the Actual Loop Rate System Channel to monitor your PCL's actual rate
      • Switch from hardware timing to software timing
        • In the System Definition, under Chassis, select None for Chassis master hardware synchronization device

      Additional Information

      • Your data acquisition is usually set to deliver data 1 value at a time to your software each iteration of the PCL
      • The problem arises when the software loop fails to pull the value before the hardware is expected to generate another value
      • Both the Primary Control Loop timing source for your controller and the Chassis master hardware synchronization device for your chassis are set to Automatic Timing by default
        •  Without any DAQ devices added, your PCL will likely rely on software timing, where the rate is determined by the software and OS of your controller
          • With software timing, the hardware should wait to be asked for a value before generating values
        • However, once you add a DAQ device, your PCL rate will default to hardware timing, where a digital signal, such as a clock on your device sets the pace.
          • A hardware clock can run much faster than a software loop which can lead to the overwrite error


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