Solution
What is the single-cycle Timed Loop?The
single-cycle Timed Loop (SCTL) is a special use of the LabVIEW Timed Loop structure. Timed Loop structures are always SCTLs when used in an FPGA VI. When used with an FPGA target this loop executes all functions inside within one tick of the FPGA clock you have selected. The default selection is the 40 MHz FPGA global clock. You can use the SCTL with derived clocks to clock the loop at a rate other than 40 MHz. You cannot dynamically change the timing properties of the Timed Loop when used with an FPGA target.
How much faster will programs execute using the SCTL?Using a traditional While Loop in your FPGA VI takes an absolute minimum of 3 ticks to execute each iteration. This is because of the enable chain used in the compiled FPGA VI. An explanation of the enable chain is beyond the scope of this document, but is used to ensure dataflow when the FPGA VI is compiled into a bitfile.
Additionally, each function inside the While Loop will require at least one tick to execute, although functions will execute in parallel if there is no data dependency. With the SCTL, all functions inside the loop must execute within a single tick.
The performance benefits of using a SCTL in your FPGA VI will vary depending on what is in the loop. If your code can compile successfully inside a SCTL instead of a normal loop, you will notice a marked performance improvement.
Is the SCTL more real estate-efficient with FPGA resources?Yes. Because your logic is implemented combinatorially in hardware, the FPGA configuration generated by the code uses less resources. Instead of doing an add, saving the result, and then a multiply and saving the result, the SCTL does both in one tick and does not have to save the result in between. This conserves FPGA resources because no flip flop is needed between operations to save the result of each previous operation.
Can all functions and structures be used inside the SCTL?No. Functions that take longer than one tick, such as analog I/O functions or any functions that wait cannot be used inside the SCTL. Also, if you have a chain of logic inside the loop that takes longer than one clock tick to execute, this logic cannot be used inside the SCTL and your VI will fail to compile.
Sequence Structures may be placed within the SCTL, but will be removed from the code before it executes on the FPGA.
The
Single-Cycle Timed Loop' help page has a list of functions that cannot be used in a SCTL. Please refer to the LabVIEW Help for more information about SCTL support and timing information for individual VIs.
- Analog Period Measurement VI
- Butterworth Filter VI
- Discrete Delay VI
- Divide function
- FIFO Clear function
- FPGA I/O Method Node except with some FPGA targets
- FPGA I/O Property Node except with some FPGA targets
- Interrupt VI
- Look-Up Table 1D VI with the Interpolate data checkbox selected
- Loop Timer VI
- Multiple FPGA I/O Nodes configured for the same I/O resource if at least one node is inside the loop and at least one node is outside the loop
- Non-reentrant subVIs if you use multiple instances
- Notch Filter VI
- PID VI
- Quotient & Remainder function
- Reciprocal function
- Rotate 1D Array function
- Sine Wave Generator VI
- Single-precision floating-point operations
- Square Root function
- Timed Loop
- Wait Express VI
- Wait on Occurrence function
- While Loop
Can I use pipelining to allow more logic to execute inside the SCTL?Yes. You can use shift registers or feedback nodes to allow logic to execute in parallel and pass data between subsequent iterations of the SCTL; thus, the entire logic chain executes over multiple SCTL iterations. As with any parallel implementation in an FPGA VI, this uses additional FPGA resources.
Will I get an error message if my logic inside the SCTL cannot execute in one tick?Yes, although LabVIEW will typically not throw timing-related errors until you attempt to compile your FPGA VI. There are two different points in your compilation where you may encounter SCTL-related errors. First, when LabVIEW FPGA attempts to compile the VI to VHDL code (Generating Intermediate Files), you will receive an error dialog box if you have used any unsupported functions (for example, Quotient and Remainder) in your SCTL. It will only take a few seconds for this box to appear (the full VHDL compilation process does not begin).
Even if you avoid using unsupported functions in your SCTL, if the SCTL contains enough logic such that the loop still can't be executed in a single clock tick, your compilation will fail with a Timing violation. This type of error occurs during the actual compilation on the Xilinx tools, and may occur several minutes (or more) into your compilation. If you run into such an error, consider either reducing the logic in your SCTL or pipelining your algorithm to allow your VI to compile successfully.
Is the SCTL an advanced feature? Yes. While some tasks can be implemented very simply in the SCTL, some can be challenging. For example, implementing high-speed digital protocols cannot be done using wait functions if using the SCTL. You must use a state machine so that each iteration of the loop will take only one tick. The SCTL provides speed and efficiency for applications that require it, but can be tricky to use. In some situations it may be more appropriate to use the traditional While Loop.
Can I use the SCTL with a faster global clock? Yes, however fewer functions can be executed in a SCTL compiled at 80 MHz or above.