cRIO-906x Disconnect Upon FPGA Reset

Updated Nov 29, 2017

Reported In


  • cRIO-9063
  • cRIO-9066
  • cRIO-9064
  • cRIO-9068
  • cRIO-9067

Issue Details

Why does my network adapter on my cRIO-9063 disconnect from the network when I reset the FPGA?


The cRIO-906x is connected to the Ethernet ports through the FPGA. Some internal components are placed in the FPGA that will be disconnected temporarily when the FPGA is reset or a new bitfile is programmed to the FPGA. 

To work around this behavior it is best to handle any errors that your network communication could exhibit when the FPGA is reset. This will be very similar to how your code should handle if the network cable was unplugged from your device.

Additional Information

This design can cause unintended behavior when resetting, opening, or closing the FPGA reference: 
Network communication can be interrupted.
Network communication can take a longer to establish when the FPGA is first programmed.


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