# Archived:Choosing Pull-Up Resistor Values for R Series Devices Digital Output Lines

Updated Nov 1, 2023

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• PCI-7831

## Issue Details

By default, the digital output lines of the R Series devices output a high value of 3.3V. According to the manual, to create a TTL signal with a 5V high on the digital output lines, I need to add an external pull-up resistor. What is the output impedance of R Series devices and what value should the pull-up resistor be?

## Solution

Note: It is not recommended or feasible to pull up the digital output from 3.3V to 5V on the PXIe 782xR, PXIe-784xR, PXIe-785xR, PXIe-786xR, and USB R Series due to the protection circuitry used in those devices.

The output impedance for the R Series devices is non-linear due to the circuitry used to provide 5V tolerance. The output impedance is low (<50 ohms) for output voltages near 0V. As the output voltage increases to around 3.3V, the impedance rises to approximately 100 ohms. As the voltage rises beyond 3.3V, the impedance rises very quickly to megohms.

Here's an approximation for how to calculate the value of pull-up resistor that you need:
1. Assume that the R Series device outputs will drive the digital output line quickly between 0V and 3.3V. The pull-up resistor will have to pull the output up from 3.3V to 5V. For a rough approximation, assume that this is a simple RC circuit where Rp is the value of your pull-up resistor, and Ctot is the total capacitance* on the digital output line. The R Series device output will be high-impedance beyond 3.3V, so it can be ignored for this calculation.
2. Solve for the value of Rp required to pull-up the output based on the timing requirements of your application. Lower values for Rp will pull-up the output faster.
3. Make sure that the value of Rp that you have chosen will not result in too much current when the R Series card is trying to drive the output low.

If you require more current sinking or sourcing ability then is provided by a single digital line, you can connect multiple digital lines together in parallel to increase the current capacity. Each line provides 4mA of current either sinked or sourced to the total current capacity of the circuit. When digital lines are connected in this way, be certain to change all of the digital line states at the same time in order to avoid damaging the R Series device. For example, in order to generate a logic high on the combined digital output, each component digital line should be changed from low to high at the exact same time in your FPGA application.

This is an example of how to calculate the pull-up resistor for a specifc application and R Series device.

Vt = 4.7V. This is the threshold level that we need to pull-up to.
DeltaT = 1us. This is the time required for the pull-up resistor to pull the digital output line from 3.3V to the 4.7V threshold level
Ctot = 100pF. Ctot represents the total capacitance on the digital output line.

The pull-up resistor, Rp, would then be:
Rp = DeltaT / ( Ctot * ( ln(1 - 3.3/5) - ln(1 - Vt/5) ) )
Rp = 1us / ( 100pF * ( ln(1 - 3.3/5) - ln(1 - 4.7/5) ) ) = 5.765 kOhms

Note: The onboard capacitance between a DO and GND is about 28pF. The cable adds about 60pF per meter.