Error -307727 When Deploying VeriStand Project

Updated May 1, 2018

Reported In


  • PXIe-4322
  • PXIe-6738


  • VeriStand 2017 Full

Issue Details

I've tried setting a DAQmx Reference Clock Source for my Timed Loop, but I receive this error when I try to deploy my project.


Check to make sure that the reference clock you are selecting has a valid path to your device's chassis backplane. You can find this information within your DAQ device routes in NI MAX.

Additional Information

This error is thrown whenever the clock you are trying to access has no valid paths to your backplane. As an example, the device routes for the PXIe-4322 show that the device does not have a valid path from the AO Sample Clock Timebase to the PXIe chassis trigger, Star, or DStarC lines.

Because the signal cannot be exported over any line except to AO Sample Clock, the signal cannot be used as a timebase for your PCL in VeriStand.

For more information on PXI(e) architecture, please visit this White Paper.


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