Issue Details
I have a VI defined FIFO in my application and I get an error message about having a read and write method in my FPGA VI. I have both read and write for the given
I am getting a Code Generation Error in my target scoped FIFO. The error details say
The VI Defined FIFO needs to have both a Read method and a Write method present on the block diagram. Add a Read function on the block diagram for this FIFO.
or
The VI Defined FIFO needs to have both a Read method and a Write method present on the block diagram. Add a Write function on the block diagram for this FIFO.
Below is an image of the error window: