Counter Output Pulse Generation Duty Cycle of 0% or 100% Causes Error -200684

Updated Apr 4, 2023

Reported In


  • VeriStand Full


  • NI-DAQmx

Issue Details

  • I am using DAQmx and LabVIEW to output a PWM signal .  However, I am unable to set the Duty Cycle to 0%.  Error -200684 occurs if I try to do so.
  • I have set up a Counter Channel with my DAQ Device in VeriStand 2012. When I set the Duty Cycle of a Pulse Generation Output to 0% or 100% Error -200684 is thrown and the VeriStand Engine stops and undeploys. 

Why does this error occur and how can I resolve it?


There is a known issue where setting the Counter Output to either 0% or 100% generates an error. This error occurs because setting a value of 0% or 100% Duty Cycle in the DAQmx task is invalid and throws an error. There are a few workarounds for this problem. 

Workaround 1:
The first workaround is to set the Duty Cycle to the next closest value supported by the specific DAQ card being used. So, instead of manually setting a value of 0.000 for 0%, you would use 0.001. And, instead of manually setting a value of 1.00 for 100%, you would set 0.999. This will stop the error from generating but is not a robust solution because it requires that the user know there is a limitation when manually setting it. The second workaround approaches this complication.

Workaround 2 (VeriStand):
The second workaround is to configure a Lookup Table Scale in the System Definition file to scale the Duty Cycle value of the counter output so that a command of 0% or 100% will never be sent to the DAQ software. It will scale the value to the closest available value automatically instead. This is the better workaround because it will prevent any invalid inputs to the Duty Cycle from either a user input or from another channel. 

Start by creating your scale in the System Explorer under the Scales section and set the Pre-scaled Values and Scaled Values as shown in the following image.

The Lookup Table Scale is setup so that if a value of 0 is selected it will scale it to .001. And, if a value of 1.00  is selected it will scale it to 0.999.

Note: At first glance the same value setting for the Pre-Scaled and Scaled values may appear to have no affect on the scaling. However, this works because values outside of the minimum and maximum range will be clipped. Please refer to the VeriStand Help: Scaling a Channel on Hardware Devices  documentation for more information on how Scaling is applied.

Next we need to apply the scale to the Duty Cycle Channel. This can be done by navigating to the channel in the System Explorer tree under the DAQ Device. Right-click on the channel and choose Select Scale. Then navigate to the Lookup Table Scale you created in the previous step. 

Your Duty Cycle channel should now be scaled to output a value of 0.001 instead of 0.000,

and a value of .999 instead of 1.000.
Workaround 3:
If an absolutely (not approximately) 0% cycle is needed for PWM, you can stop the frequency output task for the time that the 0% Duty Cycle is needed.  The task can be restarted when the value rises above 0%.

Workaround 4:
An alternate method to get an absolutely 0% duty cycle is to define the behavior via digital outputs, rather than a counter output.  Simply set the value high and low in a loop depending on the desired behavior.  This method may have performance limitations if run on a standard OS, as software timing is used.  This may result in jitter in the outputted duty cycle.  This jitter can be mitigated by running on a Real-Time operating system.  For highest performance, run on an FPGA.

Additional Information

The reason that this error is thrown is due to a limitation of the DAQ devices: the minimum duty cycle that can be set is equal to two ticks of the Timebase clock. This is why exactly 0% or 100% duty cycles are not possible.