Import or Export Clock Signal on NI 658x

Updated Jan 5, 2023



  • NI-6581
  • PXI-6581
  • NI-6583
  • NI-6588
  • PXI-6585
  • NI-6584
  • NI-6587


  • LabVIEW FPGA Module
  • LabVIEW


  • NI FlexRIO

  • I want to import or export a clock with my NI 658x adapter module. How can I configure and use these clock signals?
  • Can I import multiple clock signals with my NI 658x?

The 658x adapter modules can import and export clock signals once properly configured.  The following instructions will configure these clocks for all modules except the 6587.

​Importing Clock

You can import a clock signal through the Strobe line of the 658x cards for use in the FPGA. This clock can be used as a timing source within the FPGA code. There is one Strobe line per connector (pin 67), IO_Module_Clock0 on DDCA, and IO_Module_Clock1 on DDCB. See the following image for reference:

Configuring the Strobe Lines

  1. Right-click your FlexRIO Target in the FPGA Project and choose New » FPGA Base Clock.
  2. ​In the FPGA Base Clock Properties window, choose the name for the clock signal and configure the clock resource conditions

Using the Strobe Lines

  1. On the Functions Palette choose Structures » Timed Structures » FPGA Clock Constant:
  1. Click the dropdown menu and select the clock that was configured previously by choosing the entry with the clock's name.

Exporting a Clock

You can output a clock from your 658x adapter module on the DDC Clock Out Lines. There is one DDC Clock Out Line per connector (pin 33), DDCA Clock Out, and DDCB Clock Out. There are two signals, DDCA_ClockOut_Enable and DDCB_ClockOut_Enable, which will control if the configured clock will be exported from the FPGA.

Configuring the DDC Clock Out Lines

  1. ​Right-click your IO Module in the FPGA Project and choose Properties.
  2. Select the internal clock you want to export on each line.

Using the DDC Clock Out Lines

  1. On the Functions Palette, choose FPGA I/O » I/O Node:
  1. Set the DDCA_ClockOut_Enable or DDCB_ClockOut_Enable signal to True.

Additional Information

Because FPGA clock signals have tighter constraints and accuracy requirements than normal digital logic, clock signals can only be imported or exported via mechanisms defined in the CLIP. This means users are limited to import or export only two clock signals. If you need to access clock signals through a method other than the suggestions here, it may be possible but would require CLIP modification to define the I/O paths. This kind of modification is not supported by NI but can be done through VHDL programming. This also applies to extra functionalities like inverting the input clocks and such.