Import or Export Clock Signal on NI 658x

• I want to import or export a clock with my NI 658x adapter module. How can I configure and use these clock signals?
• Can I import multiple clock signals with my NI 658x?

The NI-658x adapter modules can import and export clock signals to be used as FPGA base clocks and/or CLIP clocks once properly configured. The following instructions will walk you through how to configure these signals. Please be aware the FPGA base clocks have hardware and software restrictions. See the Note below to understand this better.

Note: Given the hardware architecture, the PXIe-797x FPGA modules, which use the Kintex-7 FPGAs, do not have access to the external clock connector on the NI-658x adapter modules and therefore do not allow external clock sources to be used as FPGA base clocks at all. On the other hand, the PXI-795x and PXIe-796x FlexRIO FPGA Modules, which use the Virtex-5 FPGAs, allow external clock sources to be used as FPGA base clocks. Nevertheless, starting from NI FlexRIO driver version 15.0, the IO Module Clocks signals used to import external clocks to be used as an FPGA base clock in the PXI-795x and PXIe-796x cards have been deprecated. If you attempt to use the 'IO Module Clock' FPGA base clock in the FPGA VI, the compilation will fail. Therefore, if you are using the NI FlexRIO driver newer than version 15.0 with a PXI-795x or a PXIe-796x, or a PXIe-797x with any compatible version of the driver, you can only import the clock as a CLIP clock. The steps to do so are listed in the section Importing Clock as a CLIP Clock. Importing a clock source as a CLIP clock should not present any performance changes compared to importing it as an FPGA base clock. Refer to Base Clock Resources for FlexRIO Modular I/O FPGA Modules for more details on the available base clocks.  
 

​Importing Clock as an FPGA Base Clock

*Only available on PXI-795x and PXIe-796x FPGA Modules and using NI FlexRIO driver version 14.5 or older. See the Note above for a detailed explanation.

You can import a clock signal through the STROBE or GLOBAL CLK pins of the 658x module to use as an FPGA base clock. This clock can be used as a timing source within the FPGA code. There is one clock input pin per connector. You can find which pins are used for importing the external signals for each module by looking at the module's manual or CLIP reference. For example, the pins for the external clock source on the NI-6585B module would be pins 26 & 27 on each connector:
 
For the NI-6583 module, the external clock pins for the LVDS connector clock source would be pins 62 & 63. 
 

Configuring the IO Module Clock/Strobe Lines

1. Right-click your FlexRIO Target in the FPGA Project and choose New » FPGA Base Clock. 

2. ​In the FPGA Base Clock Properties window, choose the name for the clock signal and configure the clock resource conditions            

Using the IO Module Clock/Strobe Lines

1. On the block diagram of the FPGA VI, from the Functions Palette choose Structures » Timed Structures » FPGA Clock Constant:

2. Connect the FPGA Clock Constant to the input of the timed loop and use the dropdown menu and select the clock that was configured previously by choosing the entry with the clock's name.

​Importing Clock as a CLIP Clock

You can use external clocks to drive a CLIP in the same way you use other clocks your target provides. This is particularly useful if you would like to drive your CLIP with an external clock but are not able to use the external clock as an FPGA base clock (such as with the PXIe-797x modules). The variable name for the external CLIP clock changes based on which module and CLIP version you have, but can be found under the IO Module tree from the LabVIEW project window. For example, when using the NI-6585B with the 'DDR Connector' CLIP, you will use the 'DDCx_ClockIn' variable:

To use this clock in your program, you will use the same steps as mentioned in Using the IO Module Clock/Strobe Lines section from above except you will select the clock from the IO Module. For the NI-6585B using the 'DDR Connector' CLIP, it would look like this:
 

For some CLIPs, such as the 'DDR Connector' CLIP for the NI-6585B, you might also need to set this as the clock selection for the IO Module so that the signals are synchronized to a specific clock. The following steps show you how to do this using the NI-6585B with the 'DDR Connector' CLIP as an example:

1. Right-click on the IO Module and select Properties

 

2. On the Clock Selections tab, change the Connection option to match the CLIP clock

 

3. Hit OK at the bottom of the window.

 

Exporting a Clock

You can output a clock from your 658x adapter module on the DDC Clock Out Lines. There is one DDC Clock Out Line per connector (pin 33), DDCA Clock Out, and DDCB Clock Out. There are two signals, DDCA_ClockOut_Enable and DDCB_ClockOut_Enable, which will control if the configured clock will be exported from the FPGA.
 

Configuring the DDC Clock Out Lines

1. ​Right-click your IO Module in the FPGA Project and choose Properties.
2. Select the internal clock you want to export on each line.

 

Using the DDC Clock Out Lines

1. On the Functions Palette, choose FPGA I/O » I/O Node:

 

2. Set the DDCA_ClockOut_Enable or DDCB_ClockOut_Enable signal to True.

 

Additional Information

Because FPGA clock signals have tighter constraints and accuracy requirements than normal digital logic, clock signals can only be imported or exported via mechanisms defined in the CLIP. This means users are limited to importing or exporting only two clock signals. If you need to access clock signals through a method other than the suggestions here, it may be possible but would require CLIP modification to define the I/O paths. This kind of modification is not supported by NI but can be done through VHDL programming. This also applies to extra functionalities like inverting the input clocks and such.

When using the PXIe-797x FPGA Modules, or the PXI-795x and PXIe-796x FPGA Modules with the NI FlexRIO driver version 15.0 or newer, you cannot use the external clocks from the 658x as a base clock for the FPGA. However, you would be able to use an external clock from those same pins to drive the CLIP clock as a source for the timed loop on the FPGA diagram. Keep in mind that the CLIP clocks are directly driven by the external signal coming in and that there is no PLL between the external clock source and the CLIP clock. If the external clock stops, then the CLIP clock will stop along with it. This will cause an error to be thrown and stop the FPGA VI due to an attempt to read/write a control/indicator/FIFO in the CLIP clock domain while the external clock is stopped.