How Does HSDIO Data Width Affect Memory?

Updated Jun 4, 2018

Reported In


  • PXI-6562
  • PCI-6562
  • PCI-6561
  • PXI-6561
  • PXI-6542
  • PXI-6541
  • PCI-6551


  • LabVIEW

Issue Details

How does the data width with regards to my HSDIO device affect the memory allocation per channel?


Data width determines the size of each sample, and can be 1, 2, or 4 bytes. The sample size will determine the number of usable channels per device. For example, if the user configures the acquisition for a data width of 1 byte, data would be acquired on 8 channels (channels 0-7). Along the same lines, if a data width of 2 is selected, data would be acquired on 16 channels (channels 0-15). The following table illustrates this concept.
Data Width (Bytes)Number of
Channels Available

By default, the data width is always set to include all the channels on the device. For example, the NI-6541 is a 32 channel device and has a default data width of 4 bytes. The following table shows the default and valid data widths for the 654x, 655x, and 656x series. (Note that the double data rate for the 656x series only allows a data width of 1, as there are 8 channels dedicated to acquisition and 8 channels dedicated to generation). 
HSDIO DeviceDefault Data 
Width (Acquisition)
Available Data 
Widths (Acquisition)
Default Data
 Width (Generation)
Available Data Width (Generation)
PXI/PCI - 6541/241,2,444
PXIe - 6544/542,442,4
PXIe - 6547/48 SDR42,442,4
PXIe - 6547/48 DDR2222
PXI/PCI - 6551/241,2,444
PXIe - 6555/641,2,442,4
PXI/PCI - 6561/2 SDR21,222
PXI/PCI - 6561/2 DDR1111

For HSDIO acquisition and generation, the sample storage per channel is determined by the amount of available physical memory (Mb/ch) and the configured data width. Using this logic, the user may increase the number of samples that can be stored on onboard memory by reducing the data width to only include the channels needed. 
For example, suppose a user is acquiring digital data on channels 0-5 of a NI-6552 which has the 8 Mb/ch memory option, and wants to increase the onboard memory allocated to these channels. The user would want to change the data width from the default of 4 bytes to 1 byte (channels 0-7), using the HSDIO property node shown below (Property >> Advanced >> Data Width), thus increasing the memory from 8 Mb/ch to 32 Mb/ch. 
The following table shows the resulting memory size per channel by reducing the data width. 
Data Width (Bytes)Memory Size(Mb/ch)
1 Mb/ch2 Mb/ch8 Mb/ch16 Mb/ch64 Mb/ch128 Mb/ch

Additional Information

HSDIO devices contain separate acquisition and generation memory, as well as tristate and hardware compare memory (hardware compare only exists for 655x and 6547/8 devices). 

The 6547/8, 6551/2, and 6555/6 can tristate channels on a per pin, per cycle basis while generating waveforms. 

These devices store information about which channels to tristate in a section of onboard memory that is separate from the waveform data. The implementation of per pin, per cycle tristate is optimized for memory usage so that each distinct combination of channels to tristate is stored only once in memory. Thus, if a waveform tristates the same combination of channels at various samples throughout the waveform, only one memory location of the tristate memory is used. 

The 6551/2's tristate memory can store up to 4,095 distinct combinations of channels to tristate. The 6547/8 and 6555/6 can store up to 255 distinct combinations of channels to tristate.


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