VeriStand Timeout Error on Initial FPGA Deployment

Updated Apr 27, 2018

Reported In

Hardware

  • PXI Controller
  • PXI Chassis
  • PXIe-7846
  • PXI-7811
  • PXI-7813
  • PXIe-7820
  • PXIe-7821
  • PXIe-7822
  • PXI-7830
  • PXI-7831
  • PXI-7833
  • PXI-7841
  • PXI-7842
  • PXI-7851
  • PXI-7852
  • PXI-7853
  • PXI-7854
  • PXIe-7856
  • PXIe-7858
  • PXIe-7867
  • PXIe-7868

Software

  • VeriStand

Operating System

  • NI Linux Real-Time

Issue Details

When I attempt to deploy my model from VeriStand to an R-Series card I receive a timeout error on my initial deployment but when I redeploy everything runs correctly thereafter, what could be causing this to occur? 

Solution

If you are using a remote chassis you can try increasing your VeriStand gateway timeout setting or if you are using a PXIe-1085 chassis and currently have your R-Series card inserted in slots 10-18 try moving your card somewhere within slots 2-9.

From this point if you are still experiencing the same error, you transfer the FPGA IP into an FPGA Add-on Custom Device and modify the initialization sequence of the custom device to to retry opening a dynamic reference to the BIT file upon error which will force a second deployment of the BIT file. This route is not highly recommended but is a known workaround for this error.

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