Using PFI0 in the FPGA of the CompactRIO With DAQmx

Updated Aug 30, 2018

Reported In

Hardware

  • CompactRIO Controller

Software

  • LabVIEW FPGA Module
  • LabVIEW Real-Time Module
  • LabVIEW

Driver

  • NI-DAQmx

Issue Details

  • How do I interface with the PFI0 on cRIO controllers with DAQmx (cRIO-904x and cRIO-905x)
  • How do I synchronize FPGA acquisition with DAQmx acquisition?
  • How can I send the PFI0 signal on mycRIO-904x or cRIO-905x to the FPGA?

Solution

In your Real-Time VI, you can use DAQmx Connect Terminals.vi to connect the PFI0 line to one of the cRIO trigger FPGA resources. Then, in your FPGA code, you can read your cRIO trigger resource as a digital input to trigger events in your FPGA code.
 
  1. Place DAQmx Connect Terminals.vi on the block diagram of your Real-Time VI. Select PFI0 as your Source Terminal and select one of the last four cRIO trigger lines, either 4,5,6 or 7, (e.g. cRIO_Trig5) as your Destination Terminal.
  • Note: When creating DAQmx Terminal constants by right-clicking the terminal and selecting Create>>Constant, the constant fields will not populate with names unless your project is connected to the cRIO and if compatible software is loaded on the cRIO.
  • To connect to the cRIO, right-click the cRIO item in your project and select Connect.
  • Update your cRIO software, to get the compatible versions as indicated by your devices manual and specifications guide.
  • Alternatively, you can also use string inputs for source terminal and destination terminal if you cannot connect to your cRIO for the time being.
  1. Find the cRIO_Trig folder under the FPGA target in your project. This contains all of the cRIO trigger FPGA resources.
  1. Click and drag the cRIO trigger resource you have connected to PFI0 into the block diagram of your FPGA VI.
  1. You can now read the signal from your cRIO trigger resource in your FPGA VI.

Additional Information

  • To get the most accurate synchronization, NI recommends taking advantage of the FPGA resources and performing the complete acquisition in this level.
  • The shared trigger bus lines have fixed directions. The first 4 triggers go from FPGA to DAQmx and the last 4 go from DAQmx to FPGA. This is explained in the cRIO-904x/905x Considerations.
    • If you use one of the first 4 trigger bus lines in DAQmx Connect Terminals.vi, as a Source Terminal, you can use the cRIO trigger lines to output onto the PFI0.

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