Controller for FlexRIO CLIP Signals Not Listed

Updated May 15, 2018

Reported In

Hardware

  • Controller for FlexRIO

Software

  • LabVIEW FPGA Module

Issue Details

I'm creating or editing socketed CLIP for the FlexRIO 793x Controller. When I attempt to import my IP into LabVIEW, I receive synthesis errors mentioning the following signals:

aMgtRefClkEnable 
aMgtRefClkFreqSelect 


What are these signals and do I have to include them?

Solution

These two signals are not listed in the 793x User Manual but they are required CLIP signals and you will receive errors if you do not define them. The RefClkEnable signal has to have a logical '1' written to it to enable the MGT reference clock, and the RefClkFreqSelect signal allows you to write a '0' or '1' to it to change the MGT reference clock frequency between 156.25 MHz or 312.50 MHz respectively.
 

Additional Information

For an example of these signals being used, consult the example CLIP used in the 793x Aurora example, located at C:\Program Files (x86)\National Instruments\LabVIEW <year>\examples\FlexRIO\Controller for FlexRIO\NI 793xR - MGT Example Aurora CLIP\Dual_Aurora_x1_NI_793X by default.

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