What is the DSA Oversample Clock and Frequency?

Issue Details

I have seen one or more references to the oversample clock for Dynamic Signal Acquisition (DSA) devices. What is this oversample clock, why is it important, and what is its frequency?

Solution

DSA(Dynamic Signal Acquisition) devices use a special class of converters, both analog-to-digital (ADC) and digital-to-analog (DAC), known as Delta-Sigma or Sigma-Delta Converters. Many of the features that make DSA devices well-suited for frequency domain measurements are directly related to the use of delta-sigma parts. These features include excellent linearity, dynamic range, and transparent digital anti-aliasing filters. 

Unlike the converters found in traditional multifunction DAQ devices, delta-sigma converters require a special timing signal known as the oversample clock. This clock is so named because it runs a frequency many times greater than the desired sampling rate. 

On some devices, such as the NI 4472 and NI 4461/4462, the oversample clock rate is based on the requested sampling rate. Other devices, such as the NI 4464 and NI 4480/4481, have a constant oversample clock rate regardless of the requested sampling rate, and is equivalent to the modulator sample rate provided in specifications documents. 

As an example of a device with a variable oversample clock, on the NI 4472 the oversample clock runs at exactly 128 times the desired sampling rate when the sampling rate is 51.2 kS/s or less. At rates greater than 51.2 kS/s, the oversample clock runs at 64 times the sampling rate. Thus, at 51.2 kS/s or 102.4 kS/s, the oversample frequency is 6.5536 MHz (51.2k * 128 = 6.5536M, 102.4k * 64 = 6.5536M). These rates dictate some fundamental characteristics of the digital filters, as described in the NI 447x Specifications, look at the figure below.
 
For more information about Delta-Sigma ADCs and oversampling, please see the Benefits of Delta-Sigma Analog-to-Digital Conversion.

Additional Information

For synchronization between the NI 4472 and NI 4461/4462 sharing the oversample clock is an essential step in obtaining synchronization with very little phase difference between two or more devices. However, the actual clock signal that is shared by both the PCI and PXI versions of the 4472 is actually twice the oversample rate.

Thus, the clock on the PXI_Star bus in a synchronized 4472 acquisition may be as high as 13.112 MHz. If you import this signal from a counter, for instance, you must then divide it by either 128 (Fs > 51.2 kS/s) or 256 (Fs = or < 51.2 kS/s) to obtain the DSA device sample rate.

If your device does not list an oversample rate in the specifications and you must oversample, you can use the Resample Waveforms VI in your LabVIEW code.